1. Field of the Invention
The present invention relates to a package of a semiconductor chip, and more particularly to a wire-bonding package of a semiconductor chip with bonding pads arranged in an array, such as a ball grid array structure or flip chip structure.
2. Description of the Related Art
As semiconductor technique rapidly improves, the operational speed and the complexity of the semiconductor chips have increased. Accordingly, research in packaging technology comes hereafter for the requirement of higher packaging efficiency.
In a wire-bonding package of a semiconductor chip, arrangement of bonding pads on the semiconductor chip is particularly emphasized. Conductive traces on the substrate of the package, such as a ball-grid array (BGA) package, can be lithographically defined to achieve a very fine pitch. However, the bonding pad pitch is typically restricted from achieving a comparable pitch to the conductive traces due to spacing and design rules used to account for wire bonding methods and tolerances. It goes without saying that IC bonding pad design becomes a key factor of the package manufacturing efficiency.
Generally, the structure and function of the semiconductor chip determines the number of connections to external circuit elements (which can be referred to as xe2x80x9cinput-outputxe2x80x9d or xe2x80x9cI/Oxe2x80x9d connections). More specifically, a chip with powerful function has more I/O connections. Consequently, the IC bonding pad design is determined in functional consideration.
Conventional IC bonding pad designs include single in-line bonding pad design and staggered bonding pad design. It is desired to increase the maximum allowable pad number that can be designed on a chip with functional consideration, so single in-line bonding pad design is not preferred. Alternatively, the staggered bonding pad design relatively increases the maximum allowable pad number and has been used widely in general.
FIG. 1 and FIG. 2 show a conventional staggered BGA package 100. The package 100 has a chip 110 with a staggered bonding pad design (that is, two-tier type arrangement) disposed on the upper surface of a substrate 120. Further, the upper surface of the substrate 120 is provided with a ground ring 130, a power ring 140, and a plurality of conductive traces 160. The surface of the chip 110 is provided with a plurality of the bonding pads 122 positioned in two rows, as shown in FIG. 2. The bonding pads 122 on the chip 110 include power pads for supplying the source voltage, ground pads for supplying the ground potential, and signal pads (I/O pads). The bonding pads 122 are respectively connected to the ground ring 130, the power ring 140 and the conductive traces 160 by bonding wires 122a, 122b, 122c and 122d. Further, the chip 110, the bonding wires 122a, 122b, 122c and 122d, and a portion of the upper surface of the substrate 120 are encapsulated in a package body 150.
As shown in FIG. 2, the bonding wires 122a connect the outer-row bonding pads 122 that serve as the ground pads to the ground ring 130; the bonding wires 122b connect the outer row of the bonding pads 122 that serve as the power pads to the power ring 140; and the bonding wires 122c and 122d connect the outer row and the inner row of the bonding pads 122 that serve as the I/O pads to the conductive traces 160. In this conventional staggered BGA package 100, the bonding pads 122 include more I/O pads, so the ground pads and the power pads, which are connected to the ground ring 130 and the power ring 140 near the chip 110, are disposed as the outer row of the bonding pads 122. Further, at least four tiers of bonding wires with different loop heights are required to avoid short circuiting. That is, the bonding wires 122a and 122b have lower loop height than the bonding wires 122c, and the bonding wires 122c have lower loop height than the bonding wires 122d. 
However, the maximum allowable pad number that can be designed on the chip of the conventional staggered BGA package 110 is not preferable with the functional consideration. As a result, a conventional three-tier type BGA package is disclosed to further increase the maximum allowable pad number.
FIG. 3 and FIG. 4 show a conventional three-tier type BGA package 200. The package 200 has a chip 210 with a three-tier bonding pad design (that is, three-tier type arrangement) disposed on the upper surface of a substrate 220. Further, the upper surface of the substrate 220 is provided with a ground ring 230, a power ring 240, and a plurality of conductive traces 260. The surface of the chip 210 is provided with a plurality of the bonding pads 222 positioned in three rows, as shown in FIG. 4. The bonding pads 222 on the chip 110 include power pads, ground pads, and I/O pads, in which the outer row of the bonding pads 222 consist of the power pads and the ground pads, and the mid row and the inner row of the bonding pads 222 consist of the I/O pads. The bonding pads 222 are respectively connected to the ground ring 230, the power ring 240 and the conductive traces 260 by three tiers of bonding wires 222a, 222b, and 222c, in which the low-tier bonding wires 222a connect the outer row of the bonding pads 222 to the ground ring 230 or the power ring 240, and the mid-tier bonding wires 222b and the high-tier bonding wires 222c connect the mid row and the inner row of the bonding pads 222 to the conductive traces 260, as shown in FIG. 3. Further, the chip 210, the bonding wires 222a, 222b, and 222c, and a portion of the upper surface of the substrate 220 are encapsulated in a package body 250.
The conventional three-tier type BGA package 200 further increases the maximum allowable pad number that can be designed on the chip. However, the outer row of the bonding pads 222 include only the power pads and the ground pads, so the number of the power pads and the ground pads is still limited to the number of a row. Further, the bonding wires 222a, which connect the power pads or the ground pads to the power ring 240 or the ground ring 230, are disposed to be adjacent, so the inductance effect of the bonding wires leads to noise interference and causes damage to quality of signal transmission.
In view of this, the present invention relates to a package of a semiconductor chip with array-type bonding pads, which further increases the maximum allowable pad number that can be designed on the chip. That is, the chip size can be reduced with the same number of bonding pads provided on the chip, so as to reduce cost and increase package quality of the chip.
Further, the present invention relates to a package of a semiconductor chip with array-type bonding pads, in which the bonding pads has an arrangement that the bonding wires have lower inductance effect that leads to reduced noise interference.
The present invention discloses a package, which has a substrate having an upper surface, in which the upper surface of the substrate being provided with a ground ring, a power ring and a plurality of conductive traces; and a semiconductor chip disposed on the upper surface of the substrate, in which the chip has a plurality of bonding pads located about periphery of the chip, the bonding pads are positioned in at least four rows along each side of the chip, and the four rows include an inner row, a mid-inner row, a mid-outer row, and an outer row, in which the inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.
The above-mentioned package can be a flip chip structure.
Further, the package preferably has: a plurality of first bonding wires electrically connecting the outer row of the bonding pads of the chip to corresponding conductive traces of the substrate; a plurality of second bonding wires electrically connecting the mid-outer row of the bonding pads of the chip to corresponding conductive traces of the substrate; a plurality of third bonding wires electrically connecting the mid-inner row of the bonding pads of the chip to corresponding conductive traces of the substrate; a plurality of fourth bonding wires electrically connecting the inner row of the bonding pads of the chip to corresponding conductive traces of the substrate; and a package body formed over the chip, the bonding wires and the upper surface of the substrate. The package can be a ball-grid array (BGA) package.
In the above-mentioned package, it is preferable that the inner row and the mid-inner row of the bonding pads are positioned in an interlaced arrangement in relation to an edge of the chip; the mid-outer row of the bonding pads are positioned to align to the inner row of the bonding pads in a perpendicular direction to the edge of the chip; and the outer row of the bonding pads are positioned to align to the mid-inner row of the bonding pads in a perpendicular direction to the edge of the chip.
Further, the bonding pads preferably have a plurality of pad groups, each of the pad groups has an inner pad of the inner row, a mid-inner pad of the mid-inner row, a mid-outer pad of the mid-outer row, and an outer pad of the outer row of the bonding pads, in which the mid-outer pad aligns to the inner pad, and the outer pad aligns to the mid-inner pad. Further, each of the pad groups preferably has a width equal to two bonding pad pitches.
The present invention further discloses a semiconductor chip, comprising a plurality of bonding pads located about periphery of the chip, wherein the semiconductor chip is characterized at: the bonding pads being positioned in at least four rows along each side of the chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row, wherein the inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.
In the above-mentioned semiconductor chip, it is preferable that the inner row and the mid-inner row of the bonding pads are positioned in an interlaced arrangement in relation to an edge of the chip; the mid-outer row of the bonding pads are positioned to align to the inner row of the bonding pads in a perpendicular direction to the edge of the chip; and the outer row of the bonding pads are positioned to align to the mid-inner row of the bonding pads in a perpendicular direction to the edge of the chip.
Further, the bonding pads preferably have a plurality of pad groups, each of the pad groups has an inner pad of the inner row, a mid-inner pad of the mid-inner row, a mid-outer pad of the mid-outer row, and an outer pad of the outer row of the bonding pads, in which the mid-outer pad aligns to the inner pad, and the outer pad aligns to the mid-inner pad. Further, each of the pad groups preferably has a width equal to two bonding pad pitches.
Further, the above-mentioned semiconductor chip is suited to a flip chip structure or a BGA package.